1. Technical Field
Various embodiments of the present disclosure generally relate to nonvolatile memory devices and methods for operating the same and, more particularly, relate to single poly nonvolatile memory (NVM) cells, arrays thereof, and methods for operating the same.
2. Related Art
Recently, a lot of effort has been focused on applying NVM devices to memory devices embedded in system-on-chip (SOC) packages which are also referred to as SOC embedded memory devices. Typical NVM devices are fabricated using a double poly process that provides two different polysilicon layers which are vertically stacked. Thus, there may be some limitations in applying the typical NVM devices to the SOC embedded memory devices which is fabricated by a standard complementary metal-oxide-semiconductor (CMOS) process.
Fabrication of the typical NVM devices may require complicated processes including deposition steps for stacking polysilicon layers and etch steps for patterning the polysilicon layers to form a stack structure of a floating gate and a control gate. Since the typical NVM devices are fabricated to have the stack structure of the floating gate and the control gate, a probability of a misalignment between the floating gate and the control gate may increase, reducing the fabrication yield of the typical NVM devices. Accordingly, single poly NVM devices are very attractive as candidates for the SOC embedded memory devices since the single poly NVM devices can be fabricated using a standard CMOS process.